Comparison ledger
Applied Materials 0010-16392 ESC Assembly, SPTS APS, side by side. Every value shown is drawn from the cited encyclopedia entries.
| Attribute | 0010-16392 ESC AssemblyApplied Materials | APSSPTS |
|---|---|---|
| OEM | Applied Materials | SPTS |
| Category | Etch | Etch |
| Wafer size | — | — |
| Process node | — | — |
| Introduced | — | — |
| Production run | — | — |
| Lifecycle | — | — |
| Lifecycle milestones | — | — |
| Control system | — | — |
| Generation | — | — |
| Family | Applied Materials 0010-16392 ESC Assembly | SPTS APS |
| Specifications | ||
| OEM | Applied Materials[1] | — |
| Model | 0010-16392[1] | — |
| Type | ESC Assembly[1] | — |
| Wafer Size | 300 mm[2] | — |
| Electrode Configuration | Dual[2] | — |
| System type | — | ICP-based high density plasma source[3] |
| Optimization target | — | Dielectric etching[3] |
| Processing mode | — | Single wafer processing[3] |
| Clamping | — | Electrostatic clamping[3] |
| End-point detection | — | Optical Emission Spectroscopy (EOS) and laser reflectometry/interferometry[3] |
| Gases available | — | O2, Ar, CHF3, He, C4F8, SF6, H2[3] |
| Plasma source type | — | ICP (inductively coupled plasma) high density plasma source[3] |
| Available gases | — | O2 (0-100 sccm), Ar (0-100 sccm), CHF3 (0-100 sccm), He (0-500 sccm), C4F8 (0-100 sccm), SF6 (0-100 sccm & 0-500 sccm), H2 (0-50 sccm)[3] |
| Wafer clamping | — | Electrostatic clamping (no EBR required)[3] |
| Wafer voltage biasing | — | Independent from the ICP[3] |
| Process chamber | — | Single wafer processing with loadlock[3] |
| Process type | — | ICP-based high density plasma source[3] |
| Etch materials | — | Dielectrics: SiO2, SixNy, SiC, Al2O3, glass types[3] |
| Wafer bias | — | Wafer voltage biasing independent from the ICP[3] |
| Wafer handling | — | Loadlock/chamber transfers for single wafer processing[3] |
| Automation | — | Control software offering fully automated processes[3] |
| Process gases | — | O2 (0-100 sccm), He (0-500 sccm), SF6 (0-100 sccm), H2 (0-50 sccm), plus Ar, CHF3, C4F8[3] |
| Stated processes | — | BARC_Slow, Si3N4_Smooth, SiO2_PR_1:1, SiO2_PR_2:1, SiO2_PR_3:1, SiO2_PR_3:1_SOFT, SiO2_PR_5:1, SiO2_PR_soft, Pi_vertical, Pi_tapered, Fused_silica, Pyrex, LiNbO3_wafers, Chamber clean[3] |
| Chuck temperature | — | 10 °C for most processes, 20 °C for fused silica, 25 °C for Pyrex, -10 °C for LiNbO3[3] |
| Maximum etch time | — | 20 minutes for processes marked with *; longer etches are split into steps with an automatic O2 dry clean between each[3] |
| Wafer cooling check | — | Helium leak-up rate (LUR) must not exceed 200 mtorr/min[3] |
| Plasma source | — | ICP-based high density plasma source[3] |
| Wafer biasing | — | Independent from ICP[3] |
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