Vigus Nest

The Tokyo Electron Vigus Nest is a dry etch system designed for processing 300 mm wafers. The model was introduced around June 2007.^[3][2]

Dry etch systems generate a plasma from process gases inside a reaction chamber. The plasma contains reactive ions and radicals that etch the wafer surface with anisotropic or isotropic profiles depending on the process conditions. The Vigus Nest, like other plasma etchers, uses radio-frequency (RF) power to sustain the plasma and control the energy of ions bombarding the wafer.

In semiconductor manufacturing, dry etching is performed after photolithographic patterning. The resist mask defines the areas to be etched, and the dry etch process transfers that pattern into the underlying film. Dry etching is used for front-end-of-line (FEOL) and back-end-of-line (BEOL) layers, such as gate definition, contact hole etching, and metal trench formation.

The Vigus Nest is applied to etching various thin films used in integrated circuit fabrication, including silicon dioxide, silicon nitride, polysilicon, and metals. Dry etching provides the directional control required for high-aspect-ratio features in advanced logic and memory devices.